The press has been abuzz recently with the talk that Tim Mattson gave at SC10 on Intel's development of their MIC (Many Integrated Core) architecture.
There has been much speculation that Knight's Corner (KC), Intel's first implementation of the MIC architecture, is a direct competitor to NVIDIA's Fermi GPGPU and its relations. In essence this sees it as the result of the closure of the famous (or possibly infamous, depending on your point of view) Larrabee GP GPU competitor. Not that KC and its relations are GP GPUs, but they are seen as attached processors and as competing with GPGPUs in the HPC market.
That is one perspective, but the value of MIC to Intel does not really lie there. Several years back Intel announced that it had created an 80-core processor, variously known as "the Terascale chip" or as "Polaris", as part of its Terascale Computing programme, investigating the issues associated with integrating large numbers of cores on a single chip. For a long while there was speculation about whether this technology had been integrated into Larrabee. Then KC appeared, and so to the present discussion.
For Intel the Golden Rule is "Moore's Law", that device count should double roughly every two years, conventionally translated as "power" will double. The central issue has been to understand how that will happen in the multicore world. For the company the drivers are not just technological, though those are important, but market perception of future capability. That of course translates into share price.
The real value in the Terascale programme has been in learning (a) what the physical issues involved with large-scale, multicore integration are; and (b) what the corresponding software issues are. While Terascale was custom VLIW and directed to study the interconnect issues, Larrabee and KC are x86-derived, ie modified x86 and are more in a direct line of descent from earlier Intel processors.
The most important comment made during the presentation was that "the architecture is arbitrarily scalable [to] one thousand cores". That represents a huge step beyond today's levels of integration. This doesn't mean a kilocore prototype lurking inside Intel, but that their analysis shows that they have at least identified an architecture that potentially bridges the gap between the present low core-count x86 variants and high core-count systems. Since KC is supposed to be x86-compatible that presumably means that it is not simply hardware scalable, but also software scalable.
The issue for Intel with multicore has always been how to find a route that enables replacement of the standard x86 with something that is at least compatible in a way that makes software migration at least plausible for their user-base. For the biggest chip company in the world that obliges it to have a clear growth path in a way that others don't. It has far less room for manoeuvre than, say NVIDIA.
Intel are quoted as saying that their objective is to bring to the broader market place the developments that they are trialling in the HPC market. Their aim is to deal with compatibility issues in software and have "any" x86 code retargetable onto the MIC architecture.
With KC estimated to appear in early adopter sites2012, don't expect kilocore engines running Word just yet. Assuming that KC arrives on schedule and that count subsequently doubles every year then the capability to create a 1000 core engine would appear to be there sometime into the 2020s. Don't bank on it though, core doubling has so far proceeded below anticipated rates. In any case we currently only see 8 - 16 cores in market plans. However that scalability ought to take them through the next ten years or more.
For Intel the route to long term performance doubling is becoming clear. The war is very far from won but perhaps, just perhaps, a strategy is beginning to emerge.